These building blocks in clude gated D flip-lops for r educed p ower consumption,current DAC with minimized spikes,pixel cell im mune from device and process variations and large output swing.

• 这些模块包括用于降低功耗的带门D触发器,具有最小尖刺噪声的电流模式DAC,所设计的象素单元对器件和工艺的差异不敏感,并具有较大的输出范围。