The thesis expounds the cell design and timing design of the FPGA circuit in main controlling and baseband signal processing module, and develops the hardware of it, and programs part of the software.

• 文中详细阐述了主控与基带处理单元中FPGA模块设计与时序设计,研制了主控与基带信息处理单元硬件,编写了部分调试软件。