The practice shows that this method can save a lot of FPGA resources,which just need over 100 LE logic unit to effectively solve the FIR digital filter design algorithms in FPGA resource issues.

• 实践表明,此方法可以节省大量的FPGA资源,仅仅需要100多个LE逻辑单元,就可以有效解决FIR数字滤波器算法在FPGA设计中资源紧张的问题。