The field programmable gate array(FPGA) simulation shows that compared to the multiplier with Radix?8 Booth algorithm,the speed of this multiplier is increased by 11% and its hardware resource is reduced by 3%.

• 经现场可编程逻辑器件仿真验证表明；与采用Radix-8 Booth算法的乘法器相比；该乘法器速度提高了11%25；硬件资源减少了3%25.