The algorithms were used to analyze the complexity of parallel FSMs. A two-way parallel UTOPIA Level-4 interface has been designed to reduce the ten gigabit ethernet access system clock rate by one half.

• 以此方法为基础,设计了两路并行的10G以太网接入系统的utopiaLevel-4接口,使芯片所需的工作时钟频率降低了一半,从而证明此方法可以有效地应用于并行状态机的设计。