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- Stacked chip scale package 叠层芯片尺寸封装
- Finite element based solder joint fatigue life predictions for a same die stacked chip scale ball grid array package 芯片叠层球栅阵列尺寸封装的焊球疲劳寿命预测
- Stress analysis on gold wire of chip scale package 芯片尺度封装中焊线的应力分析研究
- The manufacture of solder bump is one of the key technologies for area array packaging (AAP) such as ball grid array (BGA), chip scale packaging (CSP) and flip chip (FC). 钎料凸台的制造是球栅阵列封装(BGA, ball grid array)、芯片尺寸级封装(CSP, chip scale packaging)及倒装芯片封装(FC, flip chip)等面阵封装的关键技术之一。
- Dual In-line Memory Module with Wafer Level Chip Scale Package 在内的芯片组大厂注意而成为内存模块新标准。晶圆级封装的内存模块
- W.W. Lee, L.T. Nguyen, and G.S. Selvaduray, “Solder Joint Fatigue Models: Review and Applicability to Chip Scale Packages,” Microelectronics Reliability, Vol. 40, pp. 231-244, 2000. 刘宏毅,金属受随机负载作用下之疲劳分析模式与探讨,国立台湾大学机械工程研究所硕士论文,1998。
- wafer-level chip scale packaging 圆片级芯片尺寸封装
- TVS diode Chip Scale Package 瞬态电压抑制二极管覆晶晶片微型封装
- chip scale package (CSP) 芯片尺寸封装
- Chip scale package 芯片规模封装
- CSP(Chip scale package) 芯片级封装(CSP)
- In this paper, a scheme is presented for the data acquisition system accessing internet using the S7600A (TCP/IP protocol stack chip) of Seiko Co. , Ltd. The CPU of the data acquisition is AT90S4433( AVR RISC CMOS 8 - bit singlechip). 应用一款基于AVR RISC的低功耗CMOS 8位单片机AT190S4433构成数据采集系统;利 用Seiko公司的S7600A硬件协议堆栈芯片完成通讯数据的协议封装联入INTERNET.
- Chip scale packaging 芯片规模封装技术
- The WLP technology that initiates processing from Wafer-Level and finishes in chip scale will be applicable on a daily broadening scale in plane array FCP. 在圆片规模上开始加工,结束于芯片规模的圆片级封装技术将在面型阵列倒装芯片的封装中得到日益广泛的应用。
- How much do all these figures stack up to? 这些数字的总和是多少?
- He is a great guy, a chip off the old block. 他是一位好人,就像他父亲一样。
- The floor was stacked up with books. 地板上堆满了书。
- The girl stacked the blocks with deliberation. 这个女孩从容地把砖堆砌起来。
- The boxes are stacked in a warehouse. 这些箱子被堆放在一个仓库里。
- The room was stacked with old books and magazines. 房间里堆满了旧书和旧杂志。