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- Resolution of Systematic Design Trouble with PLD Interior Phase Lock Loop. 使用PLD内部锁相环解决系统设计难题。
- Abstract：The Phase Lock Loop (PLL) Circuits are widely used in electronic systems especially in receivers. 锁相环路是在现代各种电子系统中，特别是在接收机中应用广泛的一种基本电路。
- The coupling visibilities(CV) of temperature sensor heads were measured with phase lock loop technique. 采用锁相环技术测试了各传感器的分光可见度随温度的变化关系。
- The frequency and phase lock loop has been applied for the carrier recovery of VSB transmission system in high definition TV. 目前，锁频锁相环在高清晰度电视VSB传输系统载波恢复中得到了应用。
- The signal processing circuses, including the low-noise pre-amplifier, the filter and the phase lock loop(PLL) demodulation were designed. 分析并研制了系统的信号调理电路，其中包括低噪声前置放大、滤波、锁相环解调。
- To meet the requirements of the target radio frequency (RF) hardware-in-the-loop simulation of the radio detonator, a method using a special phase lock loop (PLL) is presented. 摘要针对某型导弹无线电引信目标射频半实物仿真的需要，提出了一种特殊的环路锁相方法。
- To meet the requirements of the target radio frequency(RF) hardware-in-the-loop simulation of the radio detonator, a method using a special phase lock loop(PLL) is presented. 针对某型导弹无线电引信目标射频半实物仿真的需要,提出了一种特殊的环路锁相方法。
- One example is the phase comparator of a phase locked loop. 一个例子是相锁环状态下的相位比较器。
- Through the research of direct digital synthesizer (DDS) used as a divider in phase lock loop (PLL), a frequency synthesizer with small frequency resolution ratio and high purity frequency spectrum can be realized. 摘要通过对直接数字合成器在锁相环路中作为分频器应用的研究，使频率合成器可以在实现超细频率分辨率的同时达到高的频谱纯度。
- The PLL (phase lock loop) is realized by form of charge pump, its loop filter is passive two-order LPF. Compared to other form of active filter, this CP PLL has less noise, which does some good to its output spectrum. 微波锁相环采用电荷泵的形式,其环路滤波器为无源二阶低通滤波器,相比采用有源滤波器的锁相环,它不会附加有源噪声,而且滤波器结构简单,便于调试。
- PLL (phase lock loop) with PFD (phase-frequency detector) have been widely used in recent years.Reason for their popularity include extended tracking range, lower tracking time and low cost. 摘要锁相环(PLL)是一个闭环相位自动控制系统，能够利用一个精确且稳定的频率产生一系列频率准确的信号，为系统内部的其它模块提供稳定的高频时钟。
- In order to satisfy the flow measurement precision for big-pipe,multi-paths ultrasonic flow measurement system based FPGA(Field Programmable Gate Array) and phase lock loop(PLL) was developed. 为了满足大管径流量的测量精度,研制了基于现场可编程门阵列器件FPGA和锁相环路的多声路超声波流量测量系统。
- Phase locked loop (PLL) has been widely used in communication system. 锁相环路在通信系统中得到了广泛的应用。
- The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed. 定量分析了数字式锁相倍频器输出信号的相位抖动.
- It also incluses a phase locking loop (PLL) simulation used for frequency tracking of CMF. 还包括用于频率跟踪的锁相环仿真 ,锁相环可以极好地平滑噪声 ,跟踪频率变化 ,最终用于计算两路信号相位差。
- Design of RF Modem Based on Double Phase Lock Loop 基于双锁相环路的RF调制解调器设计
- Accurate IP Behavioral Modeling of Phase Lock Loop 一种精确的锁相环IP模块行为级建模
- TMS320F240 DSP is used to realize the digital Phase Locked Loop(PLL) and real-ize the hot-swap function of the parallel system. 采用TMS320F240型DSP芯片实现数字锁相同步,实现并联系统的热插拔功能。
- This paper discusses a method to demodulate FSK signal, on the basis of FPGA chip, by applying all- digital phase locked loop. 本文研究了一种采用全数字锁相环实现频移键控FSK信号解调的新方案。
