ModelSim simulations and FPGA verifications indicate that this module could work well at the clock frequency of 28.8MHz and demodulate the digital signal to baseband.

• ModelSim仿真和PGA验证表明；本文设计的初始解调电路在28.；8MHz的时钟频率下能正常工作；实现将数字信号解调至数字基带的功能