Jun Yang, Xuehai Zhou, Xi Li, Zhigang Wang, A Low Power ASIP Architecture with Loop Buffer, ICYCS 05, 2005是什么意思_Jun Yang, Xuehai Zhou, Xi Li, Zhigang Wang, A Low Power ASIP Architecture with Loop Buffer, ICYCS 05, 2005在线翻译_英语_读音_用法_例句