It uses RISC to calculate the LPC coefficients used to design the TNS decoding filter,and also optimizes the code. TNS decoding filter is described by Verilog HDL,and validates the whole Soc system on FPGA.

• TNS解码模块中所需要的滤波系数通过RISC指令计算并对算法进行了优化,滤波解码部分用硬件Verilog语言描述并在整个Soc系统中通过FPGA验证。