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IP core dependability 可靠性
A new IP core for LCD drivers has been designed. 介绍一种全新LCD驱动电路IP核的总体设计。
A reusable and low power RISC CPU IP core design is proposed in this paper. 研究设计了一个可重利用、低功耗的精简指令计算机 (RISC)中央处理器的知识产权 (IntellectualProper ty)核。
In FPGA module, we apply IP core technology to realizing ATA-3 protocol. 在FPGA模块中利用IP核技术实现了ATA-3协议。
This paper deals mainly with how to design the USB2.0 device IP core. 文中设计了符合USB2.;0规范的USB设备控制器IP软核。
In order to reuse easily ,this IP core uses the Avalon bus interface and completes the function simulation in Modelsim. 为了满足复用,该IP核采用Avalon总线接口,同时利用Modelsim进行了功能仿真。
The IP core is made up of four modules, which are alu_module,control_ module,timer_module and port_module. 这个IP模型主要由运算器模块，控制器模块，时钟模块和端口模块四个部分组成。
An EC bus controller of high definition television (HDTV)based on MIPS IP core is presented. 针对基于MIPS核的高清晰度电视(HDTV)的片上系统,设计了一种EC总线控制器。
The methodology of designing the eight-bit CISC microprocessor IP Core is discussed. 讨论了八位CISC微处理器IP核的设计方法。
The reuse of multimedia processor IP core is the key and difficulty of programmable media SOC design. 媒体处理器IP核重用成为可编程媒体系统芯片设计的重点和难点。
The results show that this Scaler can be taken as a correct IP core for application. 验证结果表明，该Scaler IP核可以作为功能正确的IP软核来使用。
The IP core has the function of detecting smart card, managing power, resetting, controlling reading and writing etc. 该IP核能实现对智能卡的探测、电源管理、复位和读写控制等功能。
In this paper a hardware-tailorable and software-reconfigurable USB 2.0 IP Core is proposed. 根据上述需求和实际应用的要求，本论文提出了一种硬件可裁减、软件可配置的低成本USB 2.;0数字接口引擎（SIE）的IP核。
Lastly we discuss the expand application of FFT IP core, and the implementation of high speed DCT and DST algorithmbased on FFT core. 讨论了其可以进行的应用方面的扩展，另外讨论了基于高速FFT Core的DCT和DST算法上的实现。
SDU_M08 IP Core is an 8-bit RISC MCU developed by the ASIC design centre of Information and Technology school in Shandong University. 本课题所设计的SDU_M08 IP核是山东大学信息学院集成电路研究中心所设计的一款8位RISC微控制器。
After testing the IP core which we have designed to implement the RPE-LTP speech codec algorithm, the result is satisfying. 由本课题设计实现的RPE-LTP语音编解码算法的IP Core，取得了很好的试验结果。
After that, the design flow of HMAC/SHA-1 IP core is elaborated with detailed functional module division and state machine diagram. 为了提高TPM对HMAC和SHA-1的使用效率,我们针对TPM的规范制定了设计目标,提出了一种HMAC/SHA-1的优化实现方案。
An IP core of 8051_MicroControl Unit has been designed and implemented using VHDL (VHSIC Hardware Description Language) in this thesis. 本文使用VHDL硬件描述语言，设计并实现了一个8051微控制器的IP核。
The IP core uses MASTER structure, supports WISHBONE classic cycle, advanced cycle, single read/write and block read/write. 电路采用MASTER结构，支持WISHBONE典型总线周期和改进总线周期以及单次读写和块读写周期。