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- Because of the frequency lock loop traction PLL filter can be designed very narrow, with very good noise suppression performance, to meet the precise requirements of carrier phase tracking. 由于有锁频环的频率牵引,锁相环路滤波器可以设计得很窄,具有很好的抑噪性能,满足精确跟踪载波相位的要求。
- digital frequency lock loop(DFLL) 数字锁频环
- The FLL features digital frequency locked loop (FLL) hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable multiple of the watch crystal frequency. 在FLL 功能数字频率锁定环( FLL )的硬件,与数字调制器,稳定会计频率可编程多的观赏晶体频率。
- It adopts the way of PLL (Phase Locked Loop) and FLL (frequency Locked Loop).It not only satisfies the dynamic capability and tracking precision, but also can alternate according to the environment. 在载波跟踪中,采用了PLL(锁相环)与FLL (锁频环) 结合的载波跟踪方案,使得跟踪环能够同时满足动态性能与跟踪精度的要求,且根据环境的变化使PLL和FLL交替工作。
- frequency lock loop 频率跟踪环路
- The frequency and phase lock loop has been applied for the carrier recovery of VSB transmission system in high definition TV. 目前,锁频锁相环在高清晰度电视VSB传输系统载波恢复中得到了应用。
- To meet the requirements of the target radio frequency (RF) hardware-in-the-loop simulation of the radio detonator, a method using a special phase lock loop (PLL) is presented. 摘要针对某型导弹无线电引信目标射频半实物仿真的需要,提出了一种特殊的环路锁相方法。
- To meet the requirements of the target radio frequency(RF) hardware-in-the-loop simulation of the radio detonator, a method using a special phase lock loop(PLL) is presented. 针对某型导弹无线电引信目标射频半实物仿真的需要,提出了一种特殊的环路锁相方法。
- Resolution of Systematic Design Trouble with PLD Interior Phase Lock Loop. 使用PLD内部锁相环解决系统设计难题。
- Through the research of direct digital synthesizer (DDS) used as a divider in phase lock loop (PLL), a frequency synthesizer with small frequency resolution ratio and high purity frequency spectrum can be realized. 摘要通过对直接数字合成器在锁相环路中作为分频器应用的研究,使频率合成器可以在实现超细频率分辨率的同时达到高的频谱纯度。
- Abstract:The Phase Lock Loop (PLL) Circuits are widely used in electronic systems especially in receivers. 锁相环路是在现代各种电子系统中,特别是在接收机中应用广泛的一种基本电路。
- The coupling visibilities(CV) of temperature sensor heads were measured with phase lock loop technique. 采用锁相环技术测试了各传感器的分光可见度随温度的变化关系。
- frequency locked loop 频率锁定回路
- The signal processing circuses, including the low-noise pre-amplifier, the filter and the phase lock loop(PLL) demodulation were designed. 分析并研制了系统的信号调理电路,其中包括低噪声前置放大、滤波、锁相环解调。
- The phase jitter of output signal of the PLL( phase locked loop) frequency doubler is analyzed. 定量分析了数字式锁相倍频器输出信号的相位抖动.
- FLOCK button. Pressing the Frequency Lock button will disable all frequency determining controls on the front panel, to prevent accidental changes of frequency. 频率锁定,按下这个按钮前面板所有频率控制按钮将被禁用,防止意外改变频率。
- One example is the phase comparator of a phase locked loop. 一个例子是相锁环状态下的相位比较器。
- It also incluses a phase locking loop (PLL) simulation used for frequency tracking of CMF. 还包括用于频率跟踪的锁相环仿真 ,锁相环可以极好地平滑噪声 ,跟踪频率变化 ,最终用于计算两路信号相位差。
- The basic principle of using phase locked loop technique to realize the design and analysis of program controlled frequency syntheses was introduced. 本文简要地叙述了应用锁相环路实现信号合成的基本原理。
- Phase locked loop (PLL) has been widely used in communication system. 锁相环路在通信系统中得到了广泛的应用。