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- A Clock Recovery Circuit for Fast Ethernet Application 一种快速以太网卡芯片时钟恢复电路
- Keywords GaAs;MESFET;threshold voltage;sidegating effect;fiber optic communication;decision circuit;clock recovery circuit; 阈值电压均匀性;旁栅效应;光纤通信;判决电路;时钟提取电路;
- Clock Recovery Circuit 时钟恢复电路
- In the burst mode receiver of the G bit EPON system, the clock and data recovery circuit is one of the key technologies. 摘要在吉比特级EPON的突发式接收模块中,时钟数据恢复是关键技术之一。
- clock recovery circuits 时钟恢复电路
- This thesis presents a circuit architecture to realize clock recovery for fast Ethernet application, including system architecture, modified Mueller Muller algorithm for 100BASE-TX, phase detector for 100BASE-FX and multiple output charge pump PLL. 提出了一种快速以太网卡芯片时钟恢复电路的设计 ,包括体系结构、用于 10 0BASE tx的改进MuellerMuller算法、用于 10 0BASE FX的鉴相器以及产生多相时钟的电荷泵锁相环。
- This dissertation focuses on the optical clock recovery techniques inoptical packet switching (OPS) network. 本文主要研究应用于光分组交换网络的全光时钟恢复(提取)技术。
- Data and clock recovery plays a critical part here to extract the real clock from data and retime the dirty bits. 资料与时脉回复器在此即扮演了关键角色,将时脉从接收到的资料中取出并重新取样被污染的资料。
- All Optical Bit and Frame Clock Recovery From Equal-amplitude Even-multiplexed OTDM Signals[J]. 引用该论文 尹丽娜;刘国明;曹灼;伍剑;林金桐.
- The PLL theory and the frequency of the base-band signal are analyzed for the clock recovery function of physical layer. 针对时钟恢复功能,对锁相环原理和基带信号的功率谱密度进行了分析,为时钟恢复功能的设计打下理论基础。
- To reduce the pattern effect in all-optical clock recovery, a novel device termed as code mixer was designed to preprocess the injected data signals. 为减少全光时钟提取中的码型效应,设计了混码器对注入数据脉冲进行预处理。
- Abstract: In this paper, a PLL circuits based on clock recovery system which based on phase controlled technology is studied. 摘要: 本文主要设计了基于相位控制技术的时钟恢复系统的PLL锁相环路。
- The driveing wave and energy recovery circuit (ERC) for aging system are different from SMPDP video display system. 论文在老炼电路系统的设计中,考虑到老炼时高负载和高系统稳定性的需求特点,提出一套了完全不同于视频显示系统的波形规划和能量复得维持驱动的设计方案。
- The whole SIE includes Clock Recovery, SYNC identifying, NRZI coding /decoding, Bitstuff / un-bitstuff, Cyclic Redundancy Check, Packet Identifying, Data Toggle etc. 整个串行接口引擎部分包括:时钟恢复、同步标识位识别、非归零编码/解码、比特填充/去比特填充、循环冗余校验(CRC)、分组识别、数据序列比特触发等功能模块。
- As a part of ADAS, author have designed,drew up and implemented signal processing hardware equipments and a code timing recovery circuit based PCI interface. 本课题是便携式遥测跟踪接收系统的一部分,主要完成的是遥测跟踪接收系统信号处理硬件平台的设计与实现,以及基于PCI接口的位同步器的设计与实现。
- By technique checking every operations of recovery circuit,calculating the classification of spitzkasten and cyclone,thickening efficiency,assaying the ash of every operations. 通过对太原选煤厂粗煤泥回收流程中各个作业进行技术检查,对角锥池、旋流器的分级、浓缩效率进行计算,对各个作业的灰分进行化验。
- The chapters in this book cover important topics such as jitter, eye diagrams, clock recovery, bit-error-rate (BER) testing, and stress testing for both electrical and optical communications links. 如果说有一本书可以覆盖物理层测试测量的方方面面,那么它就是《数字通信测试测量》了。
- In the design of DRC, we adopts novel 5-times dll-oversampling-based digital algorithm and look-up table skills without complex clock recovery procedure, which increased tolerance of high-speed serial data steam signal against skew and jitter. 在数据恢复电路中,论文提出了新颖的基于5-倍DLL-过采样的数字算法和查找表技术,可省去繁杂的时钟恢复过程,同时提高了高速数据信号对相位偏移(skew)和抖动(jitter)的容忍度。
- Digital method of adaptive clock recovery in circuit emulation 电路仿真中自适应时钟恢复的数字化方法
- A New Architecture High Speed Clock and Data Recovery Circuit 一种新型结构的高速时钟数据恢复电路