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- 乘法器采用改进的Booth算法,简化了部分积符号扩展,使用Wallace树结构和4-2压缩器对部分积归约。This multiplier used modified Booth Algorithm, Wallace tree and 4- 2 compressor.
- 对于SA-DCT,采用Booth算法对DCT系数编码,用可编程处理器的概念实现不同长度DCT的变换,同时提出了一种新颖的转置寄存器阵列实现所必需的转置操作,整个结构面积为12500门,最大功耗为2.54mW。Second, for the design of SA-DCT, booth encoding is introduced for coefficients of DCT, and the design concept of programmable processor is adopted to computing various-length DCT while a novel transposed register array is proposed to implement the transpose operation necessary for SA-DCT. The proposed SA-DCT core costs about 12500 gates with the maximum power consumption of 2.54mW.
- Booth算法Booth algorithm
- 算法设计algorithm design
- Booth编码Booth encoding
- 算法设计与分析The Design and Analysis of Algorithm
- Booth编码器Booth recoder
- 控制算法control algorithm
- 改进Booth编码Modified Booth encoder
- 改进的Booth编码improved Booth encoding
- 聚类算法clustering algorithm
- Booths algorithm布斯算法
- 启发式算法heuristic algorithm
- 一种新的Booth乘法器设计方法A new algorithm for design of the Booth-based multiplier unit
- 迭代算法iterative algorithm
- 双字节Booth乘法器的优化设计Architecture Optimization of Word-length Booth Multiplier
- 最优控制算法algorithm for optimal control
- Radix-16 Booth流水线乘法器的设计Design of Radix?16 Booth Pipeline Multiplier
- 渐缩算法knapsack algorithm
- 24位BOOTH乘法器核的一种有效BIST方法An Effective BIST Scheme for 24-bit BOOTH Multiplier Core