A radar target detector unit based on multi-DSP combined with FPGA was presented ,the software flow chart for system work is given and the demand speed for real-time process was estimated.

• 介绍了以多片DSP和可编程器件可编程门阵列(FPGA)相结合构成的雷达检测录取单元，给出了系统的软件流程图，分析了实时处理的速度。