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- 全数字锁相环路DPLLdigital phase locked loop
- 非平衡BPSK调制数字接收机锁相环路设计及其FPGA实现PLL Design in Digital Receiver for Nonbalanced BPSK Modulation and Realize on FPGA
- 基于VHDL语言的数字锁相环的设计与实现Design of Digital Phase Locked Loop Based on VHDL
- 延迟锁相环路delay PLL
- 数字锁相弹道相机旋转快门相位控制器的优化设计An Optimization Design for Phase Controller of Revolution Shutter in Trajectory Camera Based on DPLL
- 锁相环路稳定性PLL (Phase lock loop) stability
- 基于FPGA的数字锁控制系统VHDL设计The VHDL design of the control system of didital password lock based on FPGA
- 锁相环路PLL
- 载波快速捕获与跟踪的双数字锁频环路无缝切换Soft seamless switching in dual-loop DSP-FLL for rapid acquisition and tracking
- 锁相环phase-locked loop
- 锁相环路模块lock-oriented circuit module
- 锁相phase locking
- 模拟锁相环路simulaed phase locked loop
- 一种大频偏和低信噪比条件下的全数字锁相环设计The Design of DPLL for Low SNR Signals with Large Frequency Offset
- 锁相环路检波器phase-locked loop detector
- 锁相环路（PLL）phase locked loop(PLL)
- 数字锁相Digital lock-in
- 锁相环路同步检测phase locked loop synchronous detection
- 锁相环环路滤波器的模拟设计Simulation Design of LPF in PLL
- 锁相接收机环路参数选取的一些考虑Some Thoughts about How to Select PLL Bandwidth of Phase Lock Receiver
